1. Field of the Invention
The present invention relates to semiconductor wafers, and more particularly to a semiconductor wafer having an off-chip testing circuit for testing a die.
2. Description of the Related Art
Nowadays, in a conventional semiconductor wafer manufacturing process, an integrated circuit formed in a die (also as a chip) needs to be tested for functionality, process integrity, device behavior, and reliability, etc. FIG. 1 shows a top view of a conventional semiconductor wafer 10, the semiconductor wafer 10 comprises a plurality of dies 12 formed on die areas 14 of the semiconductor wafer 10, and the other area on the semiconductor wafer may be defined as a scribe area 16. Also, in a conventional semiconductor wafer 10, a testing circuit 18 for testing the integrated circuit of the die is also formed in the die within the die areas 14. However, because the testing circuit 18 is embodied in the die, the size of the die may be increased. In other words, the die area for the main integrated circuit is relatively reduced. Also, due to the concern of die size, the testing functions of the testing circuit may need to be reduced.
In addition, the testing circuit 18 of the conventional semiconductor wafer 10 may provide a test interface (conductive pad, conductive bump) for an external test apparatus, such that the external test apparatus may obtain the test information or test results for determining whether the tested die works. However, a hacker may uses the test interface to steal information from the integrate circuit of the die, it may be insecure. Therefore, an improved testing circuit and method is needed.